As an information processing system, the following system is known. That is, a microprocessor of a sharing memory controller included in a sharing memory device communicates, through a sharing memory bus and sharing memory ports of the sharing memory device and sharing memory interfaces of computers, with the same computers. Double control of the sharing memory device is executed by a double control circuit of the sharing memory interface selected out of the sharing memory interfaces of the computers.
Japanese Laid-Open Patent Publication No. 62-103756 discusses the prior art.